発表論文・著書

通信情報システム専攻 (CCE) > 集積システム工学講座 > 大規模集積回路分野 (ICD)

98F 98S 99 00 01 02 03 04 05 06 07

No Articles

98F 98S 99 00 01 02 03 04 05 06 07

A. Hirata, H. Onodera, K. Tamaru
Estimation of Propagation Delay Considering Short-Circuit Current forStatic CMOS Gates
IEEE Trans. on Circuits and Systems I: Fundamental Theory andApplications, 45, 1194-1198

K-M Lu, K. Tamaru
CAM-Based Array Converter for URR Floating-Point Arithmetic
IEICE Trans. Inf. & Syst., Vol.E81-D, 1120-1130

K. Tamaru, K. Kobayashi, H. Onodera
Memory Based Architecture and its Implementation Scheme NamedBit-Parallel Block-Parallel Functional Memory Type Parallel ProcessorBPBP FMPP
Computers & Electrical Engineering, 24, 17-31

M. Kondo, H. Onodera, K. Tamaru
Model-Adaptable MOSFET Parameter-Extraction Method Using an IntermediateModel
IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, Vol.17, 400-405

K. Kobayashi, N. Nakamura, K. Terada, H. Onodera, K. Tamaru
An LSI for Low Bit-Rate Image Compression Using Vector Quantization
IEICE Trans. Electron., Vol.E81-C, 718-724

近藤正樹, 小野寺秀俊, 田丸啓吉
中間モデルを用いたMOSFETの統計的モデル化手法
電子情報通信学会論文誌 A, J81-A, 1555-1563

98 99F 99S 00 01 02 03 04 05 06 07

K. Okada, H. Onodera, K. Tamaru
Layout Dependent Matching Analysis of CMOS Circuits
IEICE Trans. Fundamentals, E82-A, 348-355

K. Kobayashi, K. Terada, H. Onodera, K. Tamaru
A Real-Time Low-Rate Video Compression Algorithm Using Multi-StageHierarchical Vector Quantization
IEICE Trans. Fundamentals, E82-A, 215-222

M. Hashimoto, H. Onodera, K. Tamaru
A Power and Delay Optimization Method Using Input Reordering inCell-Based CMOS Circuits
IEICE Trans. Fundamentals, E82-A, 159-166

98 99F 99S 00 01 02 03 04 05 06 07

小野寺秀俊, 平田昭夫, 北村晃男, 小林和淑, 田丸啓吉
P2Lib: スタンダードセルライブラリ自動生成システム
情報処理学会論文誌, 40, 1660-1669

平田昭夫, 近藤友一, 小野寺秀俊, 田丸啓吉
抵抗分を含む負荷を駆動するCMOS論理回路のゲート遅延時間計算手法
情報処理学会論文誌, 40, 1679-1686

橋本昌宜,ICD, P, 岡山理科大学
グリッチの削減を考慮したゲート寸法最適化による消費電力削減手法
情報処理学会論文誌, 40, 1707-1716

98 99 00F 00S 01 02 03 04 05 06 07

Y. Fujii, D. Nagasawa, H. Nozawa, K. Kobayashi, K. Tamaru
Physical Insights on Imprint and Application to Functional Memory withFerroelectric Materials
Proceedings of the 12th International Symposium on IntegratedFerroelectrics, 33, 1313-1322

98 99 00F 00S 01 02 03 04 05 06 07

K. Kobayashi, M. Yamaoka, Y. Kobayashi, H. Onodera, K. Tamaru
Architecture and Performance Evaluation of a New Functional Memory:Functioal Memory for Addition
IEICE Transactions Fundamentals, E83-A, 2400-2408

T. Fujita, H. Onodera
A Method for Linking Process-Level Variability to System Performances
IEICE Transaction Fundamentals, E83-A, 2591-2599

M. Hahsimoto, H. Onodera
A Performance Optimization Method by Gate Resizing Based on StatisticalStatic Timing Analysis
IEICE Transaction Fundamentals, E83-A, 2558-2568

藤田智弘, 小野寺秀俊
ベクトル合成モデルによる集積回路遅延特性のワーストケース解析
情報処理学会論文誌, 41, 927-934

98 99 00 01F 01S 02 03 04 05 06 07

T. Fujita, H. Onodera
A Hierarchical Statistical Optimization Method Driven by ConstraintGeneration Based on Mahalanobis' Distance
IEICE Transactions, E84-A, 727-734

K. Kobayashi, M. Eguchi, T. Iwahashi, T. Shibayama, X. Li, K. Takai, H. Onodera
A Low-Power High-Performance Vector-Pipeline DSP for Low-Rate Videophones
IEICE Transactions on Electronics, E84-C, 193-201

K. Okada, H. Onodera
Statistical Modeling of Device Characteristics with Systematic Variability
IEICE Transacions on Fundamentals, E84-A, 529-536

98 99 00 01F 01S 02 03 04 05 06 07

T. Yasuda, H. Fujita, H. Onodera
A Dynamically Phase Adjusting PLL for Improvement of Lock-up Performance
IEICE Trans. on Fundamentals, E84-A, 2793-2801

M. Hashimoto, H. Onodera
Post-Layout Transistor Sizing for Power Reduction in Cell-Base Design
IEICE Trans. on Fundamentals, E84-A, 2769-2777

98 99 00 01 02F 02S 03 04 05 06 07

No Articles

98 99 00 01 02F 02S 03 04 05 06 07

M. Hashimoto, Hidetoshi Onodera
Increase in Delay Uncertainty by Performance Optimization
IEICE Transactions on Fundamentals, Vol.E85-A, 2799-2802

土谷 亮, 橋本 昌宜, 小野寺 秀俊
VLSI配線の伝送線路特性を考慮した駆動力決定手法
情報処理学会論文誌, Vol.43, 1338--1347

岡田 健一, 小野寺 秀俊
トランジスタ特性におけるチップ内ばらつきのモデル化手法
情報処理学会論文誌, Vol.43, 1330-1337

98 99 00 01 02 03F 03S 04 05 06 07

No Articles

98 99 00 01 02 03F 03S 04 05 06 07

K. Okada, H. Onodera
Realistic Delay Calculation Based on Measured Intra-Chip and Inter-Chip Variabilities with the Size Dependence
IEICE Trans. on Fundamentals, Vol.E86-A, 746-751

M. Hashimoto, Y. Hayashi, H. Onodera
Experimental Study on Cell-Base High-Performance Datapath Design
IEICE Trans. on Fundamentals, Vol.E86-A, 3204-3207

A. Tsuchiya, M. Hashimoto, H. Onodera
Representative Frequency for Interconnect R(f)L(f)C Extraction
IEICE Trans. on Fundamentals, Vol.E86-A, pp.2942-2951

M. Hashimoto, M. Takahashi, H. Onodera
Crosstalk Noise Estimation for Generic RC Trees
IEICE Trans. on Fundamentals, Vol.E86-A, 2965-2973

K. Okada, K. Yamaoka, H. Onodera
Statistical Gate-Delay Modeling with Intra-Gate Variability
IEICE Trans. on Fundamentals, Vol.E86-A, 2914-2922

湯山洋一, 荒本雅夫, 高井幸輔, 小林和淑, 小野寺秀俊
機能特化型プロセッサアレーによるSoCアーキテクチャの提案
電子情報通信学会論文誌 エレクトロニクス分冊, Vol.J86-C, 790-798

金本俊幾, 佐藤高史, 黒川敦, 川上善之, 岡宏規, 北浦智靖, 小林宏行, 橋本昌宜
遅延計算におけるインダクタンスを考慮すべき配線の統計的選別 手法
情報処理学会論文誌, Vol.Vol.44, pp.1301-1310

98 99 00 01 02 03 04F 04S 05 06 07

K. Kobayashi, H. Onodera
A Comprehensive Simulation and Test Environment for Prototype VLSI Verification
IEICE Trans. on Information and Systems, Vol.E87-D, 630-636

K. Kobayashi, R. Nakanishi, H. Onodera
An Efficient Motion Estimation Algorithm Using a Gyro Sensor
IEICE Trans. on Fundamentals, Vol.E87-A, 530-538

98 99 00 01 02 03 04F 04S 05 06 07

M. Hashimoto, H. Onodera
Crosstalk Noise Optimization by Post-Layout Transistor Sizing
IEICE Trans. on Fundamentals , vol E87-A, no 12, pp. 3251-3257

K. Okada, H. Hoshino, H. Onodera
Design Optimization Methodology for On-Chip Spiral Inductors
IEICE Trans. on Electronics, vol E87-C, no 6, pp. 933-941

H. Sugawara, Y. Yokoyama, S. Gomi, H. Ito, K. Okada, H. Hoshino, H. Onodera, K.Masu
Variable RF Inductor on Si CMOS Chip
Japanese Journal of Applied Physics, vol 43, no 4B, pp. 2293-2296

M. Hashimoto, Y. Yamada, H. Onodera
Equivalent Waveform Propagation for Static Timing Analysis
IEEE Trans. on CAD, vol 23, no 4, pp. 498-508

A. Higuchi, K. Kobayashi, H. Onodera
Instruction-Level Power Estimation Method by Considering Hamming Distance of Registers
IEICE Trans. on Fundamentals, vol E87-A, no 4, pp. 823-829

98 99 00 01 02 03 04 05F 05S 06 07

T. Miyazaki, M. Hashimoto, H. Onodera
A Performance Prediction of Clock Generation PLLs: A Ring Oscillator Based PLL and an LC Oscillator Based PLL
IEICE Trans. on Electronics, vol E88-C, no 3, pp. 437-444

K. Okada, H. Onodera
Statistical Parameter Extraction for Intra- and Inter-Ship Variabilities of Metal-Oxide-Semiconductor Field-Effect Transistor Characteristics
Japanese Journal of Applied Physics, vol 44, no 1A, 2005, pp. 131-134

98 99 00 01 02 03 04 05F 05S 06 07

Masanori Hashimoto, Tomonori Yamamoto, Hidetoshi Onodera
Statistical Analysis of Clock Skew Variation in H-Tree Structure
IEICE TRANS. FUNDAMENTALS, Vol.E88-A no 12, pp. 3375-3381

Takashi Sato, Masanori Hashimoto, Hidetoshi Onodera
Successive Pad Assignment for Minimizing Supply Voltage Drop
IEICE TRANS. FUNDAMENTALS, vol Vol.E88-A, no 12, pp. 3429-3436

Atsushi Muramatsu, Masanori Hashimoto, Hidetoshi Onodera
Effects of On-Chip Inductance on Power Distribution Grid
IEICE TRANS. FUNDAMENTALS, Vol.E88-A, no 12, pp. 3564-3572

K. Kishine, H. Onodera
Acquisition-time estimation for over 10 Gbit/s clock and data recovery ICs
Electronics Letters, Vol.41, no issue23, pp.1273--1275

K.Kobayashi, M.Aramoto, H.Onodera
A resource-Shared VLIW Processor for Low-power On-Chip Multiprocessing in the Nanometer Era
IEICE Trans. on Electronics , vol E88-C, no 4, pp. 552-558

T. Miyazaki, M. Hashimoto, H. Onodera
Performance Limitation of On-Chip Global Interconnects for High-Speed Signaling
IEICE Trans. on Fundamentals of Electronics, Communications ond Computer Sciences, vol E88-A, no 4, pp. 885-891

98 99 00 01 02 03 04 05 06F 06S 07

Hidetoshi Onodera
Variability: Modeling and Its Impact on Design
IEICE Trans. Fundamentals, vol E89-C, no 3, pp. 342-348

Yoichi Yuyama, Akira Tsuchiya, Kazutoshi Kobayashi, Hidetoshi Onodera
Alternative Self-Shielding for High-Speed and Reliable On-Chip Global Interconnect
IEICE Trans. Fundamentals, vol E89-A, no 3, pp. 327-333

98 99 00 01 02 03 04 05 06F 06S 07

Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera
Interconnect RL Extraction Based on Transfer Characteristics of Transmission-Line
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol E89-A, no 12, pp. 3585-3593

Toshiki KANAMOTO, Tatsuhiko IKEDA, Akira TSUCHIYA, Hidetoshi ONODERA, Masanori HASHIMOTO
Si-Substrate Modeling toward Substrate-Aware Interconnect Resistance and Inductance Extraction in SoC Design
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences, vol E89-A, no 12, pp. 3560-3568

K. Kobayashi, A. Higuchi, H. Onodera
A Leakage Reduction Scheme for Sleep Transistors with Decoupling Capacitors in the Deep Submicron Era
IEICE Transaction on Electronics, vol E89-C, no 6, pp. 838-843

98 99 00 01 02 03 04 05 06 07F 07S

No Articles

98 99 00 01 02 03 04 05 06 07F 07S

No Articles